Hardware Implementation of Modified RC4 Stream Cipher Using FPGA

— In this project work, an efficient hardware Implementation of modified RC4 stream-cipher is proposed. In contrary to previous design, which requires four memories each of size 256 X 8, the proposed system can be implemented by using only two memories each of size 128 X 7. Due to the reduction in the memory size the strength of encryption can be increased. Design of RC4 stream cipher for data Security; RC4 uses a variable length key from 1 to128 bytes to initialize a128-byte array. The array is used for subsequent generation of pseudo-random bytes and then generates a pseudorandom stream, which is XORed with the plaintext/cipher text to give the cipher text/plaintext. The RC4 stream cipher works in two phases. The key setup phase and the pseudorandom key stream generator phase. Both phases must be performed for every new key. Below is the brief about Security functions carried out at Security Layer. The RC4 algorithm will be implemented by FPGA using VHDL software platform.